 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CW18A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0 to INT4), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91CW18A CMOS 16-Bit Microcontroller TMP91CW18AF 1. Outline and Features TMP91CW18A is a high-speed 16-bit microcontroller designed for the control of various mid-to large-scale equipment. TMP91CW18AF comes in a 80-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) * * * * * Instruction mnemonics are upward-compatible with TLCS-90/900/900H 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions: Bit transfer and arithmetic instructions Micro DMA: 4 channels (640 ns /2 bytes at 25 MHz) (2) Minimum instruction execution time: 160 ns (at 25 MHz) (3) Built-in RAM: 4 Kbytes Built-in ROM: 128 Kbytes (4) External memory expansion * Expandable up to 16 Mbytes (Shared program/data area) 91CW18A-1 2005-08-15 TMP91CW18A (5) Wait controller: 1 channel (6) 8-bit timer: 8 channels (7) 16-bit timer: 1 channel (8) General-purpose serial interface (UART): 1 channel (9) Serial bus interface (I2C/Select of synchronous): 1 channel (10) Serial bus interface (I2C): 2 channels (11) 10-bit AD converter (S/H): 12 channels * Conversion time: 84 states (6.72 s at fFPH = 25 MHz) (12) Watchdog timer (13) Interrupts function * * * * * 9 CPU interrupts: Software interrupt instruction and illegal instruction 21 internal interrupts: 8 external interrupts: Seven selectable priority levels (14) Input/Output ports: 62 pins I/O: 50 pins (Programmable open drain: 12 pins) Input: 12 pins (15) Standby mode Three HALT modes: Programmable IDLE2, IDLE1, STOP (16) Clock controller * * * Clock gear: changes high-frequency clock fc to fc/16 Vcc = 4.5 V to 5.5 V (fc max = 25 MHz) P-QFP80-1420-0.80B (17) Open voltage (18) Package 91CW18A-2 2005-08-15 TMP91CW18A 25 MHz (P61) CTS /INT1 (P62) SCOUT/INT2 (P60) INT0 NMI H-OSC Port 6 X1 X2 EMU0 EMU1 RESET Interrupt controller CPU (TLCS-900/L1) XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC Port 1 F 8-bit timer (TMRA0) (P70) TA1OUT 8-bit timer (TMRA1) 8-bit timer (TMRA2) (P71) TA3OUT Port 7 8-bit timer (TMRA3) 8-bit timer (TMRA4) 8-bit timer (TMRA5) AM0 AM1 ALE AD0 (P00) AD1 (P01) AD2 (P02) AD3 (P03) AD4 (P04) AD5 (P05) AD6 (P06) AD7 (P07) AD8/A8 (P10) AD9/A9 (P11) AD10/A10 (P12) AD11/A11 (P13) AD12/A12 (P14) AD13/A13 (P15) AD14/A14 (P16) AD15/A15 (P17) A0/A16 (P20) A1/A17 (P21) A2/A18 (P22) A3/A19 (P23) A4/A20 (P24) A5/A21 (P25) A6/A22 (P26) A7/A23 (P27) RD (P30) WR (P31) HWR (P32) Watchdog timer (WDT) (P72)TA5OUT (P73) INT5/TB0IN0 (P74) INT6/TB0IN1 (P75) TB0OUT0 16-bit timer (TMRB0) 4-Kbyte RAM 3 (P76) SCK0/INT3 I C bus/SIO interface 0 2 Port 3 (P.O.D) (P80) SDA0/SO0 (P81) SCL0/SI0 (P82) TXD (P83) RXD (P84) SDA1 (P85) SCL1 (P86) SDA2 (P87) SCL2 P80 to P83 (P.O.D.), P84 to P87 (O.D.) Wait controller 8-bit timer (TMRA6) 8-bit timer (TMRA7) Port 2 Port 0 WAIT (P33) UART interface I C bus interface 1 I2C bus interface 2 2 (P34) TA6IN (P35) TA7OUT (P36) INT4 (P37) AN11 (P43) AN10 (P42) AN9 (P41) ADTRG /AN8 (P40) AN7 (P57) AN6 (P56) AN5 (P55) AN4 (P54) AN3 (P53) AN2 (P52) AN1 (P51) AN0 (P50) AVCC AVSS VREFL VREFH 128-Kbyte ROM DVCC DVCC DVSS 10-bit 12-channel AD converter Port 5 DVCC DVSS ( ): Initial function after reset Figure 1.1 TMP91CW18A Block Diagram Port 4 91CW18A-3 2005-08-15 TMP91CW18A 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91CW18A, their names and functions are as follows. 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91CW18AF. A10/AD10 (P12) A9/AD9 (P11) A8/AD8 (P10) AD7 (P07) AD6 (P06) AD5 (P05) AD4 (P04) AD3 (P03) AD2 (P02) AD1 (P01) AD0 (P00) ALE SCL2 (P87) SDA2 (P86) SCL1 (P85) SDA1 (P84) EMU1 EMU0 RESET (P13) A11/AD11 (P14) A12/AD12 (P15) A13/AD13 (P16) A14/AD14 (P17) A15/AD15 (P20) A0/A16 (P21) A1/A17 DVSS DVCC (P22) A2/A18 (P23) A3/A19 (P24) A4/A20 (P25) A5/A21 (P26) A6/A22 (P27) A7/A23 NMI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AM1 DVCC X1 DVSS X2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Top view 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DVCC AM0 (P83) RXD (P82) TXD (P81) SCL0/SI0 (P80) SDA0/SO0 (P76) SCK0/INT3 (P75) TB0OUT0 (P74) TB0IN1/INT6 (P73) TB0IN0/INT5 (P72) TA5OUT (P71) TA3OUT (P70) TA1OUT AVCC AVSS VREFL Figure 2.1.1 Pin Assignment Diagram (80-pin QFP) (P30) RD (P31) WR (P32) HWR (P33) WAIT P34 (P35) TA6IN (P36) TA7OUT (P37) INT4 (P60) INT0 (P61) CTS/INT1 (P62) SCOUT/INT2 (P50) AN0 (P51) AN1 (P52) AN2 (P53) AN3 (P54) AN4 (P55) AN5 (P56) AN6 (P57) AN7 (P40) AN8/ADTRG (P41) AN9 (P42) AN10 (P43) AN11 VREFH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ( ) : Initial function for after reset 91CW18A-4 2005-08-15 TMP91CW18A 2.2 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin Names and Functions (1/3) Pin Name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O I/O Tri-state I/O Tri-state Output Functions Port 0: I/O port that allows I/O to be selected at the bit level Address and data (Lower): Bits 0 to 7 of address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (Upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: I/O port By setting (P3 8 I/O Output Output 1 I/O Output P31 WR 1 I/O Output Port 31: I/O port Write: Strobe signal for writing data to pins AD0 to AD7 Open-drain output pin by programmable Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins AD8 to AD15 Open-drain output pin by programmable Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Open-drain output pin by programmable Port 34: I/O port Open-drain output pin by programmable Port 35: I/O port Timer A6 input Open-drain output pin by programmable Port 36: I/O port Timer A7 output Open-drain output pin by programmable Port 37: I/O port Interrupt request pin 4: Interrupt request pin with programmable rising edge/falling edge levels Open-drain output pin by programmable P32 HWR 1 I/O Output P33 WAIT 1 I/O Input P34 P35 TA6IN P36 TA7OUT P37 INT4 1 1 I/O I/O Input 1 I/O Output 1 I/O Input P40 to P43 AN8 to AN11 ADTRG 4 Input Input Input Port 40: Pin used to input port Analog input: Pin used to input to AD converter AD Trigger: Signal used to request start of AD conversion Port 5: Pin used to input port Analog input: Pin used to input to AD converter Port 60: I/O port Interrupt Request pin 0: Interrupt request pin with programmable rising edge/falling edge levels Port 61: I/O port Serial data send enable (Clear to send) Interrupt request pin 1: Interrupt request pin with programmable rising edge/falling edge levels Port 62: I/O port System clock output: Outputs fFPH or fs clock Interrupt request pin 2: Interrupt request pin with programmable rising edge/falling edge levels P50 to P57 AN0 to AN7 P60 INT0 P61 CTS 8 1 Input Input I/O Input 1 I/O Input Input INT1 P62 SCOUT INT2 1 I/O Output Input 91CW18A-5 2005-08-15 TMP91CW18A Table 2.2.2 Pin Names and Functions (2/3) Pin Name P70 TA1OUT P71 TA3OUT P72 TA5OUT P73 TB0IN0 INT5 P74 TB0IN1 INT6 P75 TB0OUT0 P76 SCK0 INT3 P80 SO0 SDA0 P81 SI0 SCL0 P82 TXD P83 RXD P84 SDA1 P85 SCL1 P86 SDA2 P87 SCL2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Number of Pins 1 I/O I/O Output I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O I/O Input I/O Output I/O I/O Input I/O I/O Output I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Port 70: I/O port Timer A1 output Port 71: I/O port Timer A3 output Port 72: I/O port Timer A5 output Port 73: I/O port Timer B0 input 0 Functions Interrupt request pin 5: Interrupt request pin with programmable rising edge/falling edge levels Port 74: I/O port Timer B0 input 1 Interrupt request pin 6: Interrupt request pin with rising edge levels Port 75: I/O port Timer B0 output 0 Port 76: I/O port Serial clock I/O 0 Interrupt request pin 3: Interrupt request pin with programmable rising edge/falling edge levels Port 80: I/O port Serial bus interface send data at SIO mode 0. 2 Serial bus interface send/receive data at I C mode 0. Open-drain output pin by programmable Port 81: I/O port Serial bus interface receive data at SIO mode 0. 2 Serial bus interface clock I/O data at I C mode 0. Open-drain output pin by programmable Port 82: I/O port Serial send data (UART) Open-drain output pin by programmable Port 83: I/O port Serial receive data (UART) Open-drain output pin by programmable Port 84: I/O port 2 Serial bus interface send/receive data at I C mode 1 N-ch FET open-drain output Port 85: I/O port 2 Serial bus interface clock I/O data at I C mode 1 N-ch FET open-drain output Port 86: I/O port 2 Serial bus interface send/receive data at I C mode 2 N-ch FET open-drain output Port 87: I/O port 2 Serial bus interface clock I/O data at I C mode 2 N-ch FET open-drain output 91CW18A-6 2005-08-15 TMP91CW18A Table 2.2.3 Pin Names and Functions (3/3) Pin Name ALE NMI Number of Pins 1 1 2 1 1 1 1 1 1 2 3 2 I/O Output Input Input Output Input Input Input Address latch enable Functions Can be disabled to reduce noise. Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable Address mode: The Vcc pin should be connected. Test pins: Open pins Reset: Initializes TMP91CW18A (with pull-up resistor). Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND pin for AD converter (0 V) I/O High-frequency oscillator connection pins Power supply pins (All Vcc pins should be connected with the power supply pin.) GND pins (All pins should be connected with GND (0V).) AM0 to AM1 EMU0, EMU1 RESET VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS 91CW18A-7 2005-08-15 TMP91CW18A 3. Operation This section describes the basic components, functions and operation of the TMP91CW18A. Notes and restrictions which apply to the various items described here are outlined in Section 7. Precautions and restrictions at the end of this databook. 3.1 CPU The TMP91CW18A incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For a description of this CPU's operation, please refer to the section of this databook which describes the TLCS-900/L1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP91CW18A. These functions are not covered in the section devoted to the TLCS-900/L1 CPU. 3.1.1 Reset When resetting the TMP91CW18A microcontroller, ensure that the power supply voltage is within the operating voltage range and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (13 s at 25 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 x 1/2). When the reset is accept, the CPU: * Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<0:7> PC<8:15> PC<16:23> * * * * Data in location FFFF00H Data in location FFFF01H Data in location FFFF02H Sets the stack pointer (XSP) to 100H. Sets bits * * * Initializes the internal I/O registers. Sets the port pins including the pins that also act as internal I/O, to general-purpose input or output port mode. Sets the ALE pin to High-Z. Note: By resetting, register in CPU except program counter (PC), status register (SR), and stack Pointer (XSP) and the data in internal RAM are not changed. Figure 3.1.1 shows the timing of a reset for the TMP91CW18A. 91CW18A-8 2005-08-15 fFPH Sampling Sampling RESET A16 to A23 (P20 to P27 input mode) ALE AD0 to AD15 (P00 to P07, P10 to P17 input mode) (P30 output mode) Address Address Read RD (Start read cycle of 0 waits after released reset) AD0 to AD15 (P00 to P07, P10 to P17 input mode) (P31 output mode) Address Data output Address Write Figure 3.1.1 TMP91CW18A Reset Timing Example 91CW18A-9 (P32 input mode) (Output mode) (Input mode) (Input mode) WR HWR P30 to P31 P32 to P33 P00 to P07, P10 to P17, P20 to P27, P34 to P37, P60 to P62, P70 to P76, P80 to P87 TMP91CW18A Pull up (Internal) High-Z 2005-08-15 TMP91CW18A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91CW18A. 000000H Internal I/O (4 Kbytes) Direct area (n) 000100H 001000H Internal RAM (4 Kbytes) 002000H 64-Kbyte area (nn) 010000H External memory 16-Mbyte area FE0000H (R) (-R) (R+) 128-Kbyte Internal ROM (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Vector table (256 bytes) ( = Internal area) Figure 3.2.1 Memory Map 91CW18A-10 2005-08-15 TMP91CW18A 3.3 Standby Function/Noise Reducing Circuit The TMP91CW18A contains (1) a clock gearing system, (2) a standby controller and (3) a noise reduction circuit. It is used for low-power and low-noise systems. This chapter is organized as follows. 3.3.1 Block Diagram of System Clock 3.3.2 SFR 3.3.3 System Clock Controller 3.3.4 Prescaler Clock Controller 3.3.5 Noise Reduction Circuits 3.3.6 Standby Controller 91CW18A-11 2005-08-15 TMP91CW18A 3.3.1 Block Diagram of System Clock The clock operating modes are as follows: Single clock mode (X1, X2 pins only) Figure 3.3.1 shows a transition figure. The clock frequency input from the X1 and X2 pins is called fc. The clock frequency selected by SYSCR1 Reset (fOSCH/32) Release reset Instruction IDLE2 mode (I/O operate) Interrupt NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Instruction IDLE1 mode (Operate only oscillator) Interrupt (a) Single clock mode transition figure Figure 3.3.1 System Clock Block Diagram 91CW18A-12 2005-08-15 TMP91CW18A SYSCR0 /2 /4 fFPH fc SYSCR0 fc/16 fSYS H-OSC /2 /4 /8 /16 Clock gear SYSCR1 fSYS TMRA01 to TMRA67 T0 Prescaler CPU ROM RAM TMRB0 Prescaler Interrupt contloller WDT I/O port UART Prescaler I2C bus 1 to 2 Prescaler SBI0 T Prescaler SCOUTC SYSCR2 Figure 3.3.2 Block Diagram of System Clock 91CW18A-13 2005-08-15 TMP91CW18A 3.3.2 SYSCR0 (00E0H) SFR 7 Bit symbol Read/Write After reset Function 1 0 1 0 High-frequency Always write oscillator (fc) 0 0: Stop 1: Oscillation 6 - 5 RXEN 4 - R/W 3 - 0 Always write 0 2 WUEF 0 Warm-up timer Write 0: Don't care Write 1: Start timer Read 0: End warm-up Read 1: Do not end warm-up 1 PRCK1 0 00: fFPH 01: Reserved 10: fc/16 11: Reserved 0 PRCK0 0 XEN High-frequency Always write oscillator (fc) 0 after release of Stop mode 0: Stop 1: Oscillation Select prescaler clock 7 SYSCR1 (00E1H) Bit symbol Read/Write After reset Function 6 5 4 3 - 0 2 GEAR2 R/W 1 1 GEAR1 0 0 GEAR0 0 Always write Select gear value of high frequency (fc) 000: fc 0 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (00E2H) Bit symbol Read/Write After reset Function 0: fs 6 SCOSEL R/W 0 1: fFPH 5 WUPTM1 R/W 1 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 DRVE R/W 0 Pin state control in STOP mode 0: I/O off 1: Remains the state before halt Warm-up timer 00: Reserved 01: 28/inputted frequency 10: 214 11: 216 Note 1: SYSCR1 91CW18A-14 2005-08-15 TMP91CW18A 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 - R/W 0 Always write 0 5 - R/W 1 Always write 1 4 - R/W 0 Always write 0 3 ALEEN R/W 0 ALE pin output control 0: High-Z output 1: ALE output 2 EXTIN R/W 0 1: External clock 1 DRVOSCH 0 - R/W 1 Always write 1 R/W 1 fc oscillator driving ability 1: Normal 0: Weak EMCCR1 (00E4H) Bit symbol Read/Write After reset Function Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0 Figure 3.3.4 SFR for Noise Reduction 91CW18A-15 2005-08-15 TMP91CW18A 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains gear circuit for high-frequency (fc) operation. The register SYSCR0 Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Time Warm-up Time SYSCR2 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to NORMAL Mode 10 (s) 0.655 (ms) 2.621 (ms) at fOSCH = 25 MHz 91CW18A-16 2005-08-15 TMP91CW18A (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0000B (SYSCR1), XXXX0100B ; ; Changes fSYS to fc/2. Changes fSYS to fc/32. X: Don't care (Changing to high-frequency clock gear) To change the clock gear, write the appropriate value to the SYSCR1 SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed (3) Internal clock pin output function The P62/SCOUT/INT2 pin outputs an internal clock: fFPH or fS. The following combination of settings - port 6 control register P6CR Table 3.3.2 SCOUT Pin States in Different Operation Modes Operation Mode SCOUT Select NORMAL, SLOW HALT mode IDLE2 IDLE1 STOP Outputs low. Fixed to 0 or 1. 91CW18A-17 2005-08-15 TMP91CW18A 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA67, TMRB0, TMRB1, SIO0, SIO1 and SBI) there is a prescaler which can divide the clock. The T clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 2. The setting of the SYSCR0 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) (2) (3) (4) Reduced driveability for high-frequency oscillator Single drive for high-frequency oscillator Disabling of ALE pin output Protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 and EMCCR1 registers. (1) Reduced driveability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) STOP C1 Resonator C2 X2 pin X1 pin Enable oscillation (STOP+EMCCR0 (Setting method) The driveability of the oscillator is reduced by writing 0 to the EMCCR0 91CW18A-18 2005-08-15 TMP91CW18A (2) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake-operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) STOP X1 pin Enable oscillation fOSCH EMCCR0 X2 pin (Setting method) When a 1 is written to the EMCCR0 Note: Do not write EMCCR0 (3) Disabling ALE pin output (Purpose) If the CPU does not access any external area, output of the ALE pulse can be disabled, thereby reduction noise. (Block diagram) EMCCR0 (Setting method) Writing 0 to the EMCCR0 91CW18A-19 2005-08-15 TMP91CW18A (4) Protection of register contents (Purpose) An item for mistake operation by inputted noise. To execute the program certainty which is occurred mistake operation, the protect register can be disabled write-operation for the specific SFR. Write disabled SFRs 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 (Block diagram) To EMCCR1 Write value other than 1FH Write 1FH Protect register EMCCR0 Write signal to the disabled SFR Write signal to the other SFR (Setting method) Writing any value other than 1FH to the EMCCR1 register turns on protection, thereby preventing the CPU from writing to the specific SFR. Writing 1FH to EMCCR1 turns off protection. The protection status is set in EMCCR0 91CW18A-20 2005-08-15 TMP91CW18A 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 Table 3.3.3 Registers of Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRA45 TMRA67 TMRB0 SIO0 (I C bus/SIO) SIO1 (I C bus) SIO2 (I C bus) UART AD converter WDT 2 2 2 SFR TA01RUN 2. 3. IDLE1: Only the oscillator continue to operate. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO, SBI AD converter WDT Interrupt controller Operation Available to select operation block. Stop IDLE2 11 Stop IDLE1 10 STOP 01 See Table 3.3.7, Table 3.3.8 Keep the state when the HALT instruction was executed. Block 91CW18A-21 2005-08-15 TMP91CW18A (2) How to clear a HALT mode The halt state can be cleared by a reset or by an interrupt request. The combination of the value in * Clearance by interrupt request Whether or not the HALT mode is cleared and subsequent operation depends on the status of the generated interrupt. If the interrupt request level set before execution of the HALT instruction is greater than or equal to the value in the interrupt mask register, the following sequence takes place. The HALT mode is cleared, the interrupt is then processed and the CPU then resumes execution starting from the instruction following the HALT instruction. If the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is not cleared. (If a non-maskable interrupt is generated, the HALT mode is cleared and the interrupt processed, regardless of the value in the interrupt mask register.) However, for NMI and INT0 to INT4 interrupts only, even if the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is cleared. In this case, the interrupt is not processed and the CPU resumes execution starting from the instruction following the HALT instruction. The interrupt request flag remains set to 1. Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to INT4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. * Clearance by reset Any halt state can be cleared by a reset. When STOP mode is cleared by a RESET signal, sufficient time (at least 3 ms) must be allowed after the reset for the operation of the oscillator to stabilize. When a HALT mode is cleared by resetting, the contents of the internal RAM remain the same as they were before execution of the HALT instruction. However, all other settings are re-initialized. (Clearance by an interrupt affects neither the RAM contents nor any other settings - the state which existed before the HALT instruction was executed is retained.) 91CW18A-22 2005-08-15 TMP91CW18A Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of Halt State Clearance NMI INTWDT INT0 to INT4 (Note 1) Interrupt INT5, INT6 INTTA0 to INTTA7 INTTB00, 01, 10, 11, OF0, OF1 INTRX0, INTRX1, TX0, TX1 INTS2 INTAD RESET Interrupt Enabled Interrupt Disabled (Interrupt level) (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE2 (Note 2) IDLE1 STOP x IDLE2 - - IDLE1 STOP - - - - *1 x x x x x x *1 x x x x x x x x x x x x x x x x x x x *1 x x x x x x Reset initializes the LSI : After clearing the HALT mode, CPU starts interrupt processing. (RESET initializes the microcontroller.) : After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. x: Cannot be used to clear the HALT mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: The HALT mode is cleared when the warm-up time has elapsed. Note 1: When the HALT mode is cleared by an INT0 to INT4 interrupt of the level mode in the interrupt enabled status, hold this level until starting interrupt processing. Changing level before holding level, interrupt processing is correctly started. Note 2: If one of the external interrupts INT5 and INT6 are generated in IDLE2 mode, TB0RUN (Example - clearing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (P6FC), 01H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ;Sets P60 to INT0 ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91CW18A-23 2005-08-15 TMP91CW18A (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.5 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 ALE AD0 to AD15 RD WR Address Data Address Address Data Clearing interrupt IDLE2 mode Figure 3.3.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC continue to operate. The system clock in the MCU stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.6 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 ALE AD0 to AD15 RD WR Address Data Address Data Clearing interrupt IDLE1 mode Figure 3.3.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91CW18A-24 2005-08-15 TMP91CW18A 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 Warm-up time X1 A0 to A23 ALE AD0 to AD15 Address Data Address Data RD WR Interrupt for release STOP mode Figure 3.3.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.6 Sample Warm-up Time after Clearance of STOP Mode at fOSCH = 25 MHz SYSCR0 0 (fc) SYSCR2 10 s 8 10 (214) 0.655 ms 11 (216) 2.621 ms 91CW18A-25 2005-08-15 TMP91CW18A Table 3.3.7 Input Buffer State Table In HALT Mode (STOP) Input Function Port Name Name During Reset P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 P20 to P27 AD16 to AD23 P30 - P31 - P32 - (Note 1) P33 WAIT (Note 1) P34 - P35 TA6IN P36 - P37 INT4 P40 to P42 AN8 to AN10 (Note 2) P43 AN11 (Note 2) ADTRG P50 to P57 AN0 to AN7 (Note 2) P60 INT0 INT1 P61 CTS P62 INT2 P70 - P71 - P72 - TB0IN0 P73 INT5 TB0IN1 P74 INT6 P75 - P76 INT3 P80 SDA0 SIO P81 SCL0 P82 - P83 RXD0 P84 SDA1 P85 SCL1 P86 SDA2 P87 SCL2 NMI - RESET - AM0, AM1 - X1 - ON ON ON ON ON: OFF: -: Note 1: Note 2: *: The buffer is always turned on. A current flows through the input buffer if the input pin is not driven. The buffer is always turned off. Not applicable Port having a pull-up/pull-down resistor. AIN input does not cause a current to flow through the buffer. AIN input is always enable. 91CW18A-26 2005-08-15 TMP91CW18A Table 3.3.8 Output Buffer State Table In HALT Mode (STOP) "H" level output Output Function Port Name Name During reset When the CPU is Operating Output Buffer State In HALT Mode (IDLE1/IDLE2) P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 (Note 1) P33 (Note 1) P34 P35 P36 P37 P40 to P7 P43 P50 to P7 P60 P61 P62 P70 P71 P72 P73 P74 P75 P76 P80 P81 P82 P83 P84 P85 P86 P87 ALE X2 AD0 to AD7 AD8 to AD15 A8 to A15 A0 to A7 A16 to A23 RD WR HWR - - - TA7OUT - - - - - - SCOUT TA1OUT TA3OUT TA5OUT - - TB0OUT0 SCK0 SDA0 SO0 SCL0 TXD0 - SDA1 SCL1 SDA2 SCL2 - - OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF - - - OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF - - OFF OFF ON ON ON ON ON ON - - - ON - - - - ON - ON ON ON ON - - ON ON ON ON ON ON ON ON ON ON ON "H" level output ON ON ON ON ON ON ON ON ON ON ON ON ON - - - ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON - - OFF ON ON: OFF: -: Note 1: A current flows through the output buffer since the buffer is always turned on. The buffer is always turned off. Not applicable Port having a pull-up/pull-down resistor. 91CW18A-27 2005-08-15 TMP91CW18A 3.4 Interrupts Interrupts are controlled by the CPU's interrupt mask register A fixed individual interrupt vector number is assigned to each interrupt source. Any one of 6 levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller transmits the interrupt source's priority value to the CPU. When more than one interrupt are generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU's interrupt mask register 91CW18A-28 2005-08-15 TMP91CW18A In addition to the general-purpose interrupt processing mode described above, there is also a micro DMA processing mode. In micro DMA mode the CPU automatically transfers data in 1-byte, 2-byte or 4-byte blocks, this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports. In addition, the TMP91CW18A also has a soft start function in which micro DMA processing is requested in software rather than by an interrupt. Figure 3.4.1 is a flowchart showing an overview of interrupt processing. Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector? Yes No Clear interrupt request flag Interrupt vector value "V" read Interrupt request F/F clear Data transfer by micro DMA General-purpose interrupt processing PUSH PC PUSH SR SR Count Count-1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA trasfer end interrupt (INTTC0 to INTTC3) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 91CW18A-29 2005-08-15 TMP91CW18A 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3) and executes only steps (2), (4) and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level have been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: The smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (Pointed to by XSP). (3) The CPU sets the value of the CPU's interrupt mask register 91CW18A-30 2005-08-15 TMP91CW18A Table 3.4.1 TMP91CW18A Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 - - 20 21 22 23 24 25 26 27 28 29 - - 32 34 35 36 37 38 - 40 41 42 43 44 - to - Maskable - Nonmaskable Type Interrupt Source or Source of Micro DMA Request Reset or instruction "SWI0" Instruction "SWI1" Illegal instruction or instruction "SWI2" Instruction "SWI3" Instruction "SWI4" Instruction "SWI5" Instruction "SWI6" Instruction "SWI7" NMI : NMI pin input Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H - - 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H - - 007CH 0084H 0088H 008CH 0090H 0094H - 009CH 00A0H 00A4H 00A8H 00ACH 00B0H to 00FCH Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H - - FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H - - FFFF7CH FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H - FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H to FFFFFCH Micro DMA Start Vector - - - - - - - - - - - 0AH 0BH 0CH 0DH 0EH 0FH 10H - - 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH - - 1FH 21H 22H 23H 24H 25H - 27H 28H 29H 2AH 2BH - to - INTWD: Watchdog timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input INT5: INT5 pin input INT6: INT6 pin input - - INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 INTTA6: 8-bit timer 6 INTTA7: 8-bit timer 7 INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) - - INTTBOF0: 16-bit timer 0 (Overflow) INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTI2C2: I C bus interface interrupt INTI2C1: I C bus interface interrupt INTSBI0: Serial bus interface interrupt - INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) - (Reserved) 2 2 91CW18A-31 2005-08-15 TMP91CW18A 3.4.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91CW18A also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU is a state of standby mode (STOP, IDLE1 and IDLE2) by HALT instruction, the requirement of micro DMA will be ignored (Pending) and DMA trandfer is started after release HALT. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The four micro DMA channels allow micro DMA processing to be set for up to four types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC3) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number. The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 3 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (e.g., interrupt requests should be disabled). If micro DMA and general-purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels.(Note) In this case, edge-triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Table 3.4.1 ) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91CW18A-32 2005-08-15 TMP91CW18A Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: 1-byte transfers, 2-byte (One-word) transfers and 4-byte transfers. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (4) "Detailed description of the transfer mode register". Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (Provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 35 different interrupts - the 34 interrupts shown in the micro DMA start vectors in Table 3.4.1 or a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode. (Micro DMA transfers are the same in every mode except counter mode.) (The conditions for this cycle are as follows: External 16-bit bus, 0 waits, and even-numbered transfer source and transfer destination addresses.) One state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Transfer source address Transfer destination address D0 to D15 Input Output Figure 3.4.2 Timing for Micro DMA Cycle States 1, 3: Instruction fetch cycle (Prefetch the next instruction) Once 3 or more bytes of code have been fetched into the instruction queue, dummy cycle is inserted into instruction fetch cycle. States 4, 5: Micro DMA read cycle State 6: Dummy cycle (The address bus remains unchanged from state 5) States 7, 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is incremented by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. Note 2: If the destination address area is an 8-bit bus, it is incremented by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. 91CW18A-33 2005-08-15 TMP91CW18A (2) Soft start function The TMP91CW18A can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once (If write "0" to each bit, micro DMA doesn't operate). On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. DMA can only be requested for one channel at once. (Therefore, do not write 1 to plural bits.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read 1, micro DMA transfer isn't started yet. When a burst is specified by the register DMAB, data is transferred continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify write instruction to avoid writing to other bits by mistake. Symbol DMAR Name DMA request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 1 DMAR1 0 0 DMAR0 0 DMA request R/W (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form "LDC cr, r" can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0. DMA destination address register 0. DMA counter register 0. DMA mode register 0. Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3. DMA destination address register 3. DMA counter register 3. DMA mode register 3. 91CW18A-34 2005-08-15 TMP91CW18A (4) Detailed description of the transfer mode register 8 bits DMAM 0 to 3 0 0 0 Mode Note: Only values whose upper 3 bits are 000 should be set in this register. Number of Minimum Execution States Execution Time (*) at fc = 25 MHz 8 states 12 states 640 ns 960 ns Number of Transfer Bytes 000 (Fixed) 000 00 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Mode Description Transfer destination address INC mode .................................................I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode .................................................I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode .................................................Memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode .................................................Memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Fixed address mode ......................................................... I/O to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 8 states 12 states 640 ns 960 ns 8 states 12 states 640 ns 960 ns 8 states 12 states 640 ns 960 ns 8 states 12 states 640 ns 960 ns Counter mode ......................For counting number of times interrupt is generated DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 5 states 400 ns *: External 16-bit bus, 0 waits, word transfer mode or 4-byte transfer mode, even-numbered transfer source and transfer destination addresses. Note: n stands for the micro DMA channel number (0 to 3) DMADn+/DMASn+: Post-increment (Register value is incremented after transfer) DMADn-/DMASn-: Post-decrement (Register value is decremented after transfer) "I/O" signifieds fixed memory addresses; "memory" signifies incremented or memory addresses. The trasnfer mode register should not be set to any value other than those listed above. 91CW18A-35 2005-08-15 TMP91CW18A 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 38 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: When a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by a 0 written to the clear bit in the interrupt priority setting register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt's vector address to the CPU. The CPU compares the mask value set in 91CW18A-36 2005-08-15 Interrupt controller Interrupt request F/F S Reset R Interrupt vector read V = 20H V = 24H CPU 1 NMI Q Reset INTWD Interrupt mask F/F Priority encoder IFF2:0 3 Interrupt level detect 3 INTRQ 2 to 0 Priority setting register Dn A Dn + 1 Interrupt Decoder B EI1 to EI7 DI Interrupt request signal to CPU D CLR C Q 1 7 3 6 6 1 INT0 to INT6 control Dn + 2 Y1 Y2 Y3 Y4 Y5 Y6 Level/edge S Reset Interrupt request flag Q Interrupt request F/F read 38 Interrupt vector generator 7 INT0 selection R Interrupt vector read Micro DMA acknowledge Dn + 3 D0 D1 2 Highest A B 3 priority interrupt C 4 level 5 select 6 If INTRQ2 to 0 IFF 2 to 0 then 1. and Rising edge/ falling edge IDLE1 STOP INT1 INT2 INT3 INT4 INT5 INT6 * selection Figure 3.4.3 Block Diagram of Interrupt Controller V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 4CH V = 50H V = 54H D2 D3 D4 D5 D6 D7 91CW18A-37 Interrupt vector read V = 9CH V = A0H V = A4H V = A8H V = ACH Micro DMA start vector setting register INTTA0 INTTA1 INTTA2 Halt release RESET INT0, INT1, INT2, INT3, INT4 NMI 4-input OR 4 if IFF = 7 then 0 0 1 2 3 A 2 2 Micro DMA request Micro DMA counter zero interrupt Soft start INTAD INTTC0 INTTC1 INTTC2 INTTC3 D CLR INTTC0 D5 D4 D3 D2 D1 D0 Q 6 Selector 34 S Reset TMP91CW18A DMA0V DMA1V DMA2V DMA3V B Micro DMA channel priority encoder Micro DMA channel specification 2005-08-15 *: Only rising edge TMP91CW18A (1) Interrupt priority setting registers Symbol INTE0AD Name Address INT0 & INTAD enable INT1 & 90H 7 IADC R 0 I2C R 0 I4C R 0 I6C R 0 ITA1C R 0 ITA3C R 0 ITA5C R 0 ITA7C R 0 6 INTAD IADM2 0 INT2 I2M2 0 INT4 I4M2 0 INT6 I6M2 0 ITA1M2 0 ITA3M2 0 ITA5M2 0 ITA7M2 0 5 IADM1 R/W 0 I2M1 R/W 0 I4M1 R/W 0 I6M1 R/W 0 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 ITA7M1 R/W 0 4 IADM0 0 I2M0 0 I4M0 0 I6M0 0 ITA1M0 0 ITA3M0 0 ITA5M0 0 ITA7M0 0 3 I0C R 0 I1C R 0 I3C R 0 I5C R 0 ITA0C R 0 ITA2C R 0 ITA4C R 0 ITA6C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 I5M2 0 ITA0M2 0 ITA2M2 0 ITA4M2 0 ITA6M2 0 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W 0 ITA6M1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 I5M0 0 ITA0M0 0 ITA2M0 0 ITA4M0 0 ITA6M0 0 INTE12 INT2 enable INT3& 91H INTE34 INT4 enable INT5 & 92H INTE56 INT6 enable INTTA0 93H INTTA1 (TMRA1) 95H INTTA0 (TMRA0) INTETA01 & INTTA1 enable INTTA2 & INTTA3 enable INTTA4 & INTTA5 enable INTTA6 & INTTA7 enable INTTA3 (TMRA3) 96H INTTA2 (TMRA2) INTETA23 INTTA5 (TMRA5) 97H INTTA4 (TMRA4) INTETA45 INTTA7 (TMRA7) 98H INTTA6 (TMRA6) INTETA67 lxxM2 0 0 0 0 1 1 1 1 Interrupt request flag lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91CW18A-38 2005-08-15 TMP91CW18A Symbol Name Address Interrupt INTETB0 enable TMRB0 Interrupt INTETB0 OV enable TMRB0 (Over flow) INTE UART Interrupt enable UART Interrupt INTES2 enable I C2 Interrupt INTES1 enable I C1 & SBI INTTC0 INTETC 01 & INTTC1 enable INTTC2 INTETC 23 & INTTC3 enable A1H A0H 2 2 7 ITB01C R 0 6 5 4 3 ITB00C R 0 ITF0C 2 1 0 INTTB01 (TMRB0) 99H ITB01M2 ITB01M1 ITB01M0 R/W 0 0 0 (Reserved) 9BH R 0 INTTX0 9CH ITX0C R 0 0 ITX0M2 ITX0M1 R/W 0 0 (Reserved) 9DH R 0 INTI2C1 9EH INTI2C1C II2C1M2 R 0 ITC1C R 0 ITC3C R 0 0 0 INTTC3 ITC3M2 ITC3M1 R/W 0 0 ITC3M0 ITC2C R 0 0 INTTC1 ITC1M2 ITC1M1 R/W 0 0 ITC1M0 ITC0C R 0 II2C1M1 R/W 0 0 II2C1M0 IS0C R 0 ITX0M0 IRX0C R 0 INTTB00 (TMRB0) ITB00M2 ITB00M1 ITB00M0 R/W 0 ITF0M2 0 INTRX0 IRX0M2 0 INTI2C2 INTI2C2C II2C2M2 0 INTSBI0 IS0M2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 ITC2M1 R/W 0 0 ITC2M0 ITC0M1 R/W 0 0 ITC0M0 IS0M1 R/W 0 0 IS0M0 II2C2M1 R/W 0 0 II2C2M0 IRX0M1 R/W 0 0 IRX0M0 0 ITF0M1 R/W 0 0 0 ITF0M0 INTTBOF0 (TMRB0) lxxM2 0 0 0 0 1 1 1 1 Interrupt request flag lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91CW18A-39 2005-08-15 TMP91CW18A (2) External interrupt control Symbol Name Address 7 - Interrupt IIMC input mode control 0 Always write 0 6 I4EDGE 0 0: Rising 1: Falling 5 I3EDGE 0 0: Rising 1: Falling 4 I2EDGE W 3 I1EDGE 0 0: Rising 1: Falling 2 I0EDGE 0 0: Rising 1: Falling 1 I0LE 0 edge mode 1: INT0 level mode 0 NMIREE 0 1: Operates even on rising + falling edge of NMI 8CH (Prohibit RMW) 0 0: Rising 1: Falling INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 INT0 level enable 0 1 0 1 Edge detect INT High level INT INT request generation at falling edge INT request generation at rising/falling edge NMI rising edge enable Setting for external interruption inputs Interrupt Request Pin Pin Name NMI - Mode Falling edge Falling/rising edge Rising edge Falling edge High level Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Condition IIMC INT0 P60 INT1 INT2 INT3 INT4 INT5 INT6 P61 P62 P76 P37 P73 P74 (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH INT0 Symbol Name Address Interrupt INTCLR clear control 88H (Prohibit RMW) Clears interrupt request flag. 5 CLRV5 0 7 6 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 Interrupt vector 91CW18A-40 2005-08-15 TMP91CW18A (4) Micro DMA start vector registers These registers assign micro DMA processing to an interrupt sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel's micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) Symbol Name Address DMA0 DMA0V start vector DMA1 DMA1V start vector DMA2 DMA2V start vector DMA3 DMA3V start vector 83H 82H 81H 80H 7 6 5 DMA0V5 0 DMA1V5 0 DMA2V5 0 DMA3V5 0 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 2 DMA0V2 0 DMA0V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0 start vector R/W DMA1 start vector R/W DMA2 start vector R/W DMA3 start vector R/W (5) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name Address DMA DMAR software request register DMA DMAB burst register 8AH 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 0 2 DMAR2 R/W 0 DMAB2 R/W 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 1: DMA software request 1: DMA burst request 91CW18A-41 2005-08-15 TMP91CW18A (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid the above program, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (e.g., "NOP" x 1 times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register INT0 level mode In level mode INT0 is not an edge-triggered interrupt, hence in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to ; edge mode. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. ; Wait EI instruction Note: INT0: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. (High Low) INTRX: Instructions which read the receive buffer. 91CW18A-42 2005-08-15 TMP91CW18A 3.5 Port Functions The TMP91CW18A features 62-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2 lists I/O registers and their specifications. Table 3.5.1 Port Functions (OD: = Open drain) (R: = with programmable pull-up resistor) (POD: = Programmable open drain) Port Name Port 0 Port 1 Port 2 Pin Name P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 P33 P34 P35 P36 P37 Number of Pins 8 8 8 1 1 1 1 1 1 1 1 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - POD OD Direction Setting Unit Bit Bit Bit Pin Name for Internal Function AD0 to AD7 AD8 to AD15/A8 to A15 A16 to A23/A0 to A7 RD WR HWR WAIT Port 3 Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit TA6IN TA7OUT INT4 AN8 to AN11, ADTRG (P40) AN0 to AN7 INT0 INT1/ CTS INT2/SCOUT TA1OUT TA3OUT TA5OUT TB0IN0/INT5 TB0IN1/INT6 TB0OUT0 INT3/SCK0 SDA0/SO0 SCL0/SIO TXD RXD SDA1 SCL1 SDA2 SCL2 Port 4 Port 5 Port 6 P40 to P43 P50 to P57 P60 P61 P62 P70 P71 P72 Port 7 P73 P74 P75 P76 P80 P81 P82 P83 P84 P85 P86 P87 Port 8 Bit Bit Bit Bit Bit Bit Bit Bit 91CW18A-43 2005-08-15 TMP91CW18A Table 3.5.2 I/O Registers and Their Specifications (1/2) Port Port 0 Name P00 to P07 Specification Input port Output port AD bus (AD0 to AD7) Input port Output port AD bus (AD8 to AD15) A output (A8 to A15) Input port Output port A output (A0 to A7) A output (A16 to A23) Input port Output port Outputs RD only when accessing an external area Always output RD Input port Output port Outputs WR only when accessing an external area Input port (without pull up) Input port (with pull up) Output port HWR output WAIT input (without pull up) WAIT input (with pull up) Output port Input port Output port Input port Output port TA6IN input Input port Output port TA7OUT output Input port Output port INT4 input Input port AN input (AN8 to AN11) (Note 1) ADTRG input (Note 2) Input port AN input (AN0 to AN7) (Note 1) Input port Output port INT0 input Input port Output port INT1 input CTS input Input port (SCOUT I/O registers Pn x x x x x x x x x x x x x 1 0 x x x 0 1 x x 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x PnCR 0 1 x 0 1 0 1 0 1 0 1 0 1 None 0 1 None 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 None None 0 1 0 0 1 0 0 0 1 0 1 PnFC None 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 0 1 None None None 0 0 1 0 0 1 Port 1 P10 to P17 Port 2 P20 to P27 P30 P31 P32 Port 3 P33 P34 P35 P36 P37 P40 to P43 P40 Port 5 P50 to P57 P60 Port 4 Port 6 P61 P62 (Note 4) 0 0 1 0 0 1 0 0 0 1 0 X: Don't care 91CW18A-44 2005-08-15 TMP91CW18A Table 3.5.3 I/O Registers and Their Specifications (2/2) Port Port 7 Name P70 Input port Output port TA1OUT output P71 Input port Output port TA3OUT output P72 Input port Output port TA5OUT output P73 Input port Output port Specification I/O registers Pn x x x x x x x x x PnCR 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 PnFC 0 0 1 0 0 1 0 0 1 None (IIEC x x x x x x x x x INT5/TB0IN0 input P74 Input port Output port INT6/TB0IN1 input P75 Input port Output port TB0OUT0 output P76 Input port Output port SCK0 input/output INT3 input Port 8 (Note 5) P80 Input port Output port SDA0 input SO0 output P81 Input port Output port SCL0 input/output SI0 input P82 Input port Output port TXD output P83 Input port Output port RXD input P84 Input port Output port SDA1 input/output P85 Input port Output port SCL1 input/output P86 Input port Output port SDA2 input/output P87 Input port Output port SCL2 input/output None 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 None 0 0 1 0 0 1 0 0 1 0 0 1 (IIEC x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x X: Don't care 91CW18A-45 2005-08-15 TMP91CW18A Note 1: When P50 to P57 are used as AD converter input channels, a 3-bit field in the AD mode control register ADMOD1 91CW18A-46 2005-08-15 TMP91CW18A 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port each bit can be individually for input or output using the control register P0CR. Resetting resets all bits of P0CR to 0 and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 can also function as an address data bus (AD0 to AD7), allowing access to external memory. In this case, all bits in the control register P0CR are cleared to 0. Reset Direction control (on bit basis) P0CR write Internal data bus Output latch Output buffer P0 write Port 0 P00 to P07 (AD0 to AD7) P0 read Figure 3.5.1 Port 0 91CW18A-47 2005-08-15 TMP91CW18A 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and the function register P1FC. Resetting resets all bits of the output latch P1, the control register P1CR and the function register P1FC to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an address data bus (AD8 to AD15) or an address bus (A8 to A15). Reset Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus P1FC write Output latch Output buffer P1 write Port 1 P10 to P17 (AD8 to AD15/A8 to A15) P1 read Figure 3.5.2 Port 1 91CW18A-48 2005-08-15 TMP91CW18A Port 0 Register 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Data from external port (Output latch register becomes undefined.) Port 1 Register 7 P0CR (0002H) Bit symbol Read/Write After reset Function 0 0: Input P07C 6 P06C 0 5 P05C 0 4 P04C W 0 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 1: Output (at external access, port 0 becomes AD7 to AD0 and P0CR is cleared to 0.) Port 0 I/O setting 0 Input 1 Output Port 1 Register 7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 P17C 6 P16C 0 5 P15C 0 4 P14C W 0 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 < 7 P1FC (0005H) Bit symbol Read/Write After reset Function 0 P17F 6 P16F 0 5 P15F 0 4 P14F W 0 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8 Port 1 function setting P1FC Read-modify-write instructions are prohibited for registers P0CR, P1CR and P1FC. 0 Input port Output port 1 Address data bus (AD15 to AD8) Address bus (A15 to A8) Note: Figure 3.5.3 Registers for Ports 0 and 1 91CW18A-49 2005-08-15 TMP91CW18A 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and the function register P2FC. Resetting set all bits of the output latch P2 to "1", the control register P2CR and the function register P2FC to 0 and sets port 2 to input mode. In addition to functioning as a general-purpose I/O port, port 2 can also function as an address bus (A0 to A7) or (A16 to A23). A16 to A23 A0 to A7 Reset Selector S B A Y Direction control (on bit basis) P2CR write Function control (on bit basis) Internal data bus P2FC write S Output latch A Selector B Y Output buffer Port 2 P20 to P27 (A0 to A7/A16 to A23) P2 write P2 read Figure 3.5.4 Port 2 91CW18A-50 2005-08-15 TMP91CW18A Port 2 Register 7 P2 (0006H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Data from external port (Output latch register is set to 1.) Port 2 Control Register 7 P2CR (0008H) Bit symbol Read/Write After reset Function 0 P27C 6 P26C 0 5 P25C 0 4 P24C W 0 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 < 7 P2FC (0009H) Bit symbol Read/Write After reset Function Note: Read-modify-write instructions are prohibited for P2CR and P2FC. 0 P27F 6 P26F 0 5 P25F 0 4 P24F W 0 3 P23F 0 2 P22F 0 1 P21F 0 0 P20F 0 P2FC/P2CR = 00: Input, 01: Output, 10: A7 to A0, 11: A23 to A16 Port 2 function setting P2FC 0 Input port Output port 1 Address bus (A7 to A0) Address bus (A23 to A16) Note: Figure 3.5.5 Registers for Port 2 91CW18A-51 2005-08-15 TMP91CW18A 3.5.4 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output. I/O is set using the control register P3CR and the function register P3FC. Resetting sets all bits of the output latch P3 and bit 0 and bit 1 of control register P3CR to 1. Bit 2 to bit 7 of P3CR are set to 0. All bits of the control register P3CR (P30C, P31C sets to 1, P32C to P37C resets to 0) and the function register P3FC (of which bits 3, 4 and 5 are unused) are cleared to 0. Resetting also causes P30 and P31 to output 1, sets P32 to P33 to input mode and turns on the pull-up resistor. And also, when output port is set, each bit is able to be set as open-drain port by P3ODE. In addition to functioning as a general-purpose I/O port, port 3 can also function as the I/O for the CPU's control/status signal. When the P30 pin is set for RD signal output mode ( 91CW18A-52 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write RD , WR A S Selector P30 ( RD ), P31( WR ) B S Selector P3 read B A Figure 3.5.6 Port 3 (P30, P31) 91CW18A-53 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write HWR A S Selector P32 ( HWR ) B S Selector P3 read B A Figure 3.5.7 Port 3 (P32) 91CW18A-54 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus S Output latch P3 write P33 ( WAIT ) S Selector P3 read B A WAIT Figure 3.5.8 Port 3 (P33) 91CW18A-55 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus S Output latch P3 write P34 S Selector P3 read B A Figure 3.5.9 Port 3 (P34) 91CW18A-56 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus S Output latch P3 write P35 (TA6IN) S Selector P3 read B A TA6IN Figure 3.5.10 Port 3 (P35) 91CW18A-57 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write TA7OUT A S Selector P36 (TA7OUT) B S Selector P3 read B A Figure 3.5.11 Port 3 (P36) 91CW18A-58 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write P37 (INT4) S Selector P3 read INT4 INT4 control B A Figure 3.5.12 Port 3 (P37) 91CW18A-59 2005-08-15 TMP91CW18A Port 3 Register 7 P3 (0007H) Bit symbol Read/Write After reset Function - 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 1 0 P30 1 P37 Data from external port (Output latch register is set to 1.) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register) : Pull-up resistor ON - Port 3 Control Register 7 P3CR (000AH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Input P37C 6 P36C 5 P35C 4 P34C W 0 1: Output I/O setting 0 Input 1 Output 0 1 1 3 P33C 2 P32C 1 P31C 0 P30C Port 3 Function Register 7 P3FC (000BH) Bit symbol Read/Write After reset Function 0 0: Port 1: INT4 P37F W 0 0: Port 1: TA7OUT 0 0: Port 1: HWR 6 P36F 5 4 3 2 P32F 1 P31F W 0 0: Port 1: WR 0 0: Port 1: RD 0 P30F P30 ( RD ) function setting 0 0 output RD is always 1 1 output RD is only TA7OUT setting 1 P3FC INT4 setting 1 1 output (for pseudo SRAM). output during external accesses. P31( WR ) function setting Note 1: Read-modify-write instructions are prohibited for registers P3CR and P3FC. Note 2: When port 3 is used in Input mode, the P3 register controls the built-in pull-up resistor. Read-modify-write instructions are prohibited in input mode or I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When the P33/ WAIT pin is to be use as the WAIT pin, P3CR 0 0 output 1 1 output P3FC 1 0 WR is only output during external accesses. HWR setting P3FC 1 P3CR Figure 3.5.13 Register for Port 3 (1/2) 91CW18A-60 2005-08-15 TMP91CW18A 7 P3ODE (002DH) Bit symbol Read/Write After rest Function 0 P37ODE 6 P36ODE 0 5 P35ODE 0 4 P34ODE 0 0: Normal R/W 3 P33ODE 0 1: Open drain 2 P32ODE 0 1 P31ODE 0 0 P30ODE 0 Setting to open drain 0 Normal 1 Open drain Figure 3.5.14 Register for Port 3 (2/2) 91CW18A-61 2005-08-15 TMP91CW18A 3.5 3.5.5 Port 4 (P40 to P43) Port 4 is a 4-bit input port and can also be used as the analog input pins for the internal AD converter. P40 is also used as the AD trigger input pin of AD converter. Port 4 Internal data bus Port 4 read P40 to P43 (AN8 to AN11) AD read Conversion result register AD converter Channel selector ADTRG (for P40 only) Figure 3.5.15 Port 4 7 P4 Bit symbol After reset (000CH) Read/Write 6 5 4 3 P43 2 P42 R 1 P41 0 P40 Data from external port Note: The input channel selection of AD converter and the permission of ADTRG (P40) input are set by AD converter mode register ADMOD1. Figure 3.5.16 Register for Port 4 91CW18A-62 2005-08-15 TMP91CW18A 3.5.6 Port 5 (P50 to P57) Port 5 is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. Port 5 Internal data bus Port 5 read P50 to P57 (AN0 to AN7) AD read Conversion result register AD converter Channel selector Figure 3.5.17 Port 5 7 P5 (000DH) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R 3 P53 2 P52 1 P51 0 P50 Data from external port Figure 3.5.18 Register for Port 5 91CW18A-63 2005-08-15 TMP91CW18A 3.5.7 Port 6 (P60 to P62) Port pins 60 to 62 constitute a 3-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 6 to be an input port. It also sets all bits of the output latch to 1. In addition to functioning as a general-purpose I/O port, port pins 60 to 62 can also function the external interrupt INT0 to INT2 input, CTS input, SCOUT output function. The various functions can each be enabled by writing a 1 to the corresponding bit of the Port 6 function register (P6FC) or SCOUT control register (SCOUTC). Resetting resets all bits of the registers P6CR and P6FC to 0 and sets all bits to be input port pins. (1) Port pin 60 (INT0) Port pin 60 is a general-purpose I/O port pin. It can also be used as the external interrupt INT0 input pin. Reset Direction control (on bit basis) P6CR write Direction function (on bit basis) Internal data bus P6FC write Output latch Output buffer P6 write P60 (INT0) P6 read INT0 INT0 control Figure 3.5.19 Port 60 91CW18A-64 2005-08-15 TMP91CW18A (2) Port pin 61 ( CTS /INT1) Port pin 61 is a general-purpose I/O port pin. It can also be used as the external INT1 input pin or as the CST input pin (in UART mode). Reset Direction control (on bit basis) P6CR write Direction control Internal data bus (on bit basis) P6FC write S Output latch P6 write P6 read INT1 control INT1 CTS0 P61 ( CTS /INT1) S B selector A Figure 3.5.20 Port 61 91CW18A-65 2005-08-15 TMP91CW18A (3) Port pin 62 (INT2/SCOUT) Port pin 62 is a general-purpose I/O port pin. It can also be used as the external interrupt INT2 input pin or SCOUT output pin function. Reset Direction control (on bit basis) P6CR write SCOUTC (on bit basis) Internal data bus SCOUTE SCOUTC write Direction control (on bit basis) P6FC write S Output latch P6 write S Y P6 read fFPH clock INT2 B Selector A S P62 (SCOUT/INT2) A Y Selector B INT2 control Figure 3.5.21 Port 62 91CW18A-66 2005-08-15 TMP91CW18A Port 6 Register 7 P6 (0012H) Bit symbol Read/Write After reset 6 5 4 3 2 P62 1 P61 R/W 0 P60 Data from external port (Output latch register is set to 1.) Port 6 Control Register 7 P6CR (0014H) Bit symbol Read/Write After reset Function 0 6 5 4 3 2 P62C 1 P61C W 0 0: Input 1: Output 0 P60C 0 Port 6 I/O setting 0 1 Input Output Port 6 Function Register 7 P6FC (0015H) Bit symbol Read/Write After reset Function 6 5 4 3 2 P62F W 0 0: Port 1: INT2 1 P61F W 0 0: Port 1: INT1 0 P60F W 0 0: Port 1: INT0 Note: Read-modify-write instructions are prohibited for the registers P6CR, P6FC and SCOUT. P60 INT0 input setting P6FC SCOUT Control Register 7 SCOUTC (001DH) Bit symbol Read/Write After reset Function 6 5 4 3 2 SCOUTE W 0 0: Port 1: SCOUT 1 0 output P62 SCOUT output setting SCOUT Figure 3.5.22 Registers for Port 6 91CW18A-67 2005-08-15 TMP91CW18A 3.5 3.5.8 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 7 to be an input port. And the output latch register P7 (All bit) set to 1. In addition to functioning as a general-purpose I/O port, P70, P71 and P72 also functions as an 1, 3, 5 output (TA1OUT, TA3OUT and TA5OUT) of the 8-bit timer A, and port pins 73 and 74 can function as the 16-bit timer clock input INT5 and INT6 input, TB0IN0/INT5 and TB0IN1/INT6. P75 as 16-bit timer output (TB0OUT0), P76 as I/O function of the serial interface 0 (SCK0). For each of the output pins, timer output can be enabled by writing a 1 to the corresponding bit in the port 7 function register (P7FC). SCK0 output function become available when a proper bit of port 7 function register P7FC is 1 and a proper bit of interrput control register IIEC is 0. To use TB0IN0/INT5, TB0IN1/INT6 and SCK0/INT3 pin as external interrupt input pins,a proper bit of interrupt enable register IIEC must be set 1. By reset, a value of P7CR, P7FC and IIEC become 0 and all bits become input mode. 91CW18A-68 2005-08-15 TMP91CW18A Reset Direction control (on bit basis) P7CR write IIEC (on bit basis) INT5E, INT6E IIEC write S Output latch P7 write P7 read INT5/TB0IN0 INT6/TB0IN1 Internal data bus INT5/TB0IN0 control lINT6/TB0IN1 control Reset Direction control (on bit basis) S B P73 (TB0IN0, INT5) P74 (TB0IN1, INT6) Selector A P7CR write IIEC (on bit basis) INT3E IIEC write Direction control (on bit basis) P7FC write S Output latch A P7 write SCK0 Timer F/F OUT TA1OUT: Timer A1 TA3OUT: Timer A3 TA5OUT: Timer A5 TB0OUT0: Timer B0 S P70 (TA1OUT) P71 (TA3OUT) P72 (TA5OUT) P75 (TB0OUT0) P76 (SCK0, INT3) Selector B B Selector P7 read SCK0 input INT3 S A INT3 control Figure 3.5.23 Port 7 91CW18A-69 2005-08-15 TMP91CW18A Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset 6 P76 5 P75 4 P74 3 P73 R/W 2 P72 1 P71 0 P70 Data from external port (Output latch register is set to 1.) Port 7 Control Register 7 P7CR (0016H) Bit symbol Read/Write After reset 0 0 0 6 P76C 5 P75C 4 P74C 3 P73C W 0 0: Input 2 P72C 0 1: Output 1 P71C 0 0 P70C 0 Port 7 I/O setting 0 1 Input Output Port 7 Function Register 7 P7FC (0017H) Bit symbol Read/Write After reset Function 0 0: Port 1: SCK0 6 P76F W 5 P75F 0 0: Port 1: TB0OUT0 4 3 2 P72F 0 0: Port 1: TA5OUT 1 P71F W 0 0: Port 1: TA3OUT 0 P70F 0 0: Port 1: TA1OUT Note 1: Read-modify-write instructions are prohibited for the registers P7CR and P7FC. Setting P70 as TA1OUT P7FC Note 2: P73/TB0IN1/INT5, P74/TB0IN/INT6 pin dose not have a register changing port/function. For example, when it is used as an input port, the timer B0 input 0,1 or INT5, INT6 are inputted to 16-bit timer B0. Figure 3.5.24 Port 7 Registers (1/2) 91CW18A-70 2005-08-15 TMP91CW18A Interrupt Enable Control Register 7 IIEC (001CH) Bit symbol Read/Write After reset Function 6 INT3E W 0 0: Port 1: INT3 5 4 INT6E W 0 0: Port 1: INT6 TB0IN1 3 INT5E 0 0: Port 1: INT5 TB0IN0 2 1 0 Note: Read-modify-write instruction is prohibited for the IIEC. Setting P73 as TB0IN0/INT5 input IIEC Setting P74 as TB0IN1/INT6 input Figure 3.5.25 Port 7 Registers (2/2) 91CW18A-71 2005-08-15 TMP91CW18A 3.5.9 Port 8 (P80 to P87) Port 8 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 8 to be an input port. It also sets all bits in the output latch register P8 to P1.Besides I/O function, each port can be used both as another function port as follows P80, P81 are used both as I/O pin SDA0/SO0, SCL0/SIO of I2C bus/SIO. P82, P83 are used both as I/O pin TXD, RXD of UART. P84 and P85 are used both as I/O pin of SDA1, SCL1 of I2C bus 1. P86, P87 are used both as I/O pin SDA2, SCL2 of I2C bus 2. These functions can be enabled by writing a 1 to the corresponding bits in the port 8 function register (P8FC). And also, when the output is set for each bit, open-drain is selectable by P8ODE. Resetting resets all bits of the registers P8CR and P8FC to 0, and sets all bits to be input port pins. Reset O.D. control (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write SDA0_out/SO0 A S P80 (SDA0/SO0) Selector B SB Selector P8 read SDA0_in A Figure 3.5.26 Port 8 (P80) 91CW18A-72 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write SCL0_out A S P81 (SCL0/SI0) Selector B SB Selector P8 read SCL0_in/SI0 A Figure 3.5.27 Port 8 (P81) 91CW18A-73 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write TXD A S P82 (TXD) Selector B SB Selector P8 read A Figure 3.5.28 Port 8 (P82) 91CW18A-74 2005-08-15 TMP91CW18A Reset O.D. contorl (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Internal data bus S Output latch P8 write P83 (RXD) SB Selector P8 read RXD A Figure 3.5.29 Port 8 (P83) 91CW18A-75 2005-08-15 TMP91CW18A Reset Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write SDA1_out SCL1_out SDA2_out SCL2_out A S Selector B P84 (SDA1) P85 (SCL1) P86 (SDA2) P87 (SCL2) SB Selector P8 read SDA1_in SCL1_in SDA2_in SCL2_in A Figure 3.5.30 Port 8 (P84 to P87) 91CW18A-76 2005-08-15 TMP91CW18A Port 8 Register 7 P8 Bit symbol (0018H) Read/Write After reset P87 6 P86 5 P85 4 P84 R/W 3 P83 2 P82 1 P81 0 P80 Data from external port (Output latch register is set to 1.) Port 8 Control Register 7 P8CR Bit symbol (001AH) Read/Write After reset Function Note: Read-modify-write instructions are prohibited for registers P8CR, P8FC and P8ODE. P87C 0 6 P86C 0 5 P85C 0 4 P84C W 0 3 P83C 0 2 P82C 0 1 P81C 0 0 P80C 0 0: Input 1: Output Port 8 I/O setting 0 1 Input Output Port 8 Function Register 7 P8FC Bit symbol (001BH) Read/Write After reset Function P87F 0 0: Port 1: SCL2 function 6 P86F W 0 0: Port 1: SDA2 function 5 P85F 0 0: Port 1: SCL1 function 4 P84F 0 0: Port 1: SDA1 function 3 2 P82F 0 0: Port 1 P81F W 0 0: Port function 0 P80F 0 0: Port 1: SDA0 function SO0 output 1: TXD output 1: SCL0 Setting P80 as SDA0/SO0 function P8FC Setting P82 as TXD output function Figure 3.5.31 Port 8 Registers (1/2) 91CW18A-77 2005-08-15 TMP91CW18A Port 8 Open-drain Enable Register 7 P8ODE Bit symbol (002FH) Read/Write After reset Function 6 5 4 3 P83ODE 0 2 P82ODE R/W 0 0: Normal 1 P81ODE 0 1:Open drain 0 P80ODE 0 Setting to open drain 0 1 Normal Open drain Figure 3.5.32 Port 8 Registers (2/2) 91CW18A-78 2005-08-15 TMP91CW18A 3.6 Wait Controller On the TMP91CW18A, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). TMP91CW18A does not have the chip select signal for the specified address area. In using TMP91CW18A, if chip select signal is needed for each memory space, user have to generate chip select signals by making a external circuit (Address decoder circuit) in order to access external ROM/RAM. 4 blocks address areas are defined by memory start address register MSAR0 to MSAR3 and memory address mask register MAMR0 to MAMR3. The wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin which controls these states is the bus wait request pin ( WAIT ). (After this chapter, 4 block address spaces are described as CS0 space, CS1 space, CS2 space and CS3 space.) 3.6.1 Specifying an Address Area The address areas CS0 to CS3 are specified using the memory start address registers (MSAR0 to MSAR3) and the memory address mask registers (MAMR0 to MAMR3). During each bus cycle, a compare operation is performed to determine whether or not the address specified on the bus corresponds to a location in one of the areas CS0 to CS3. If the result of the comparison is a match, it indicates that the corresponding CS area is to be accessed. If so, the bus cycle proceeds according to the settings in the corresponding B0CS to B3CS wait control register. (See 3.6.2 "Wait Control Registers".) 91CW18A-79 2005-08-15 TMP91CW18A (1) Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The 8 most significant bits (A23 to A16) of the start address should be set in MSAR0 (00C8H) MSAR2 (00CCH) MSAR1 (00CAH) MSAR3 (00CEH) Bit symbol Read/Write After reset Function 1 1 1 1 S23 6 S22 5 S21 4 S20 R/W 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.6.1 Memory Start Address Register Address 000000H Start address 64 Kbytes 000000H 010000H 020000H 030000H 040000H 050000H 060000H to FF0000H Value in start address register (MSAR0 to MSAR3) 00H 01H 02H 03H 04H 05H 06H to FFH FFFFFFH Figure 3.6.2 Relationship between Start Address and Start Address Register Value 91CW18A-80 2005-08-15 TMP91CW18A (2) Memory address mask registers Figure 3.6.3 shows the memory address mask registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0 to MAMR3) which is set to 1 masks the corresponding bit of the start address which has been set in the corresponding memory start address register (MSAR0 to MSAR3). The compare operation used to determine whether or not a bus address is in one of the areas CS0 to CS3 only compares address bits for which a 0 has been set in the corresponding bit position in the corresponding memory address mask register. Also, the address bits which each memory address mask register can mask vary from register to register; hence, the possible size settings for the areas CS0 to CS3 differ accordingly. Memory Address Mask Register (for CS0 area) 7 6 5 4 3 2 1 0 MAMR0 (00C9H) Bit symbol Read/Write After reset 1 1 1 1 V20 V19 V18 V17 R/W 1 1 1 1 V16 V15 V14 to V9 V8 Function Sets size of CS0 area 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1) 7 6 5 4 3 MAMR1 (00CBH) Bit symbol Read/Write After reset 1 1 1 1 V21 V20 V19 V18 R/W 1 V17 2 V16 1 1 V15 to V9 1 0 V8 1 Function Sets size of CS1 area 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) 7 6 5 4 3 MAMR2 (00CDH) MAMR3 (00CFH) Bit symbol Read/Write After reset 1 1 1 1 V22 V21 V20 V19 R/W 1 V18 2 V17 1 1 V16 1 0 V15 1 Function Sets size of CS2 or CS3 area 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.6.3 Memory Address Mask Registers 91CW18A-81 2005-08-15 TMP91CW18A (3) Setting memory start addresses and address areas Figure 3.6.4 shows an example in which CS0 is specified to be a 64-Kbyte address area starting at 010000H. First, MSAR0 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address CS0 area size (64 Kbytes) S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 H Memory start address V14 to V9 V8 V20 V19 V18 V17 V16 V15 MAMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.6.4 Example Showing How to Set the CS0 Area A reset sets MSAR0 to MSAR3 and MAMR0 to MAMR3 to FFH. In addition, B0CS 91CW18A-82 2005-08-15 TMP91CW18A (4) Address area size specification Table 3.6.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A "" indicates that it is not possible to set the area size in question using the memory start address register and memory address mask register. If an area size for a CS area marked "" in the table is to be set, the start address must either be set to 000000H or to a value that is greater than 000000H by an integer multiple of the desired area size. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the lowest-numbered CS area has highest priority (e.g., CS0 has a higher priority than any other area). Example: To set the area size for CS0 to 128 Kbytes: (1) Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. (2) Invalid start addresses 000000H 010000H 030000H 050000H 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.6.1 Valid Area Sizes for Each CS Area Size (Bytes) CS Area CS0 CS1 CS2 CS3 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M 91CW18A-83 2005-08-15 TMP91CW18A 3.6.2 Wait Control Registers Figure 3.6.5 lists the wait control registers. The master enable/disable, data bus width and number of wait states for each address area (CS0 to CS3 plus any other) are set in the respective wait control registers, B0CS to B3CS or BEXCS. Wait Control Register 7 B0CS Bit symbol B0E (00C0H) Read/Write W Read-modify- After reset 0 write Function 0: Disable instructions 1: Enable are prohibited. 6 5 - 0 Always write 0 4 - 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 1 B0W1 0 100 0 B0W0 0 010: (1 + N) waits 110 111 B1W2 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 Invalid settings B1CS Bit symbol B1E - 0 Always write 0 - 0 B1BUS 0 Data bus width 0: 16 bits 1: 8 bits B1W1 0 B1W0 0 (00C1H) Read/Write W Read-modify- After reset 0 write Function 0: Disable instructions 1: Enable are prohibited. 010: (1 + N) waits 110 111 B2W2 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 Invalid settings B2CS Bit symbol B2E B2M 0 CS2 area selection 0: 16-Mbyte area 1: CS area - 0 Always write 0 - W 0 B2BUS 0 Data bus width 0: 16 bits 1: 8 bits B2W1 0 B2W0 0 (00C2H) Read/Write Read-modify- After reset 1 write Functions 0: Disable instructions 1: Enable are prohibited. 010: (1 + N) waits 110 111 B3W2 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 111 101 Invalid settings B3CS Bit symbol B3E - 0 Always write 0 - 0 B3BUS 0 Data bus width 0: 16 bits 1: 8 bits B3W1 0 B3W0 0 (00C3H) Read/Write W Read-modify- After reset 0 write Functions 0: Disable instructions 1: Enable are prohibited. 010: (1 + N) waits 110 BEXW2 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 111 BEXW1 0 Invalid settings BEXCS Bit symbol BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits BEXW0 0 (00C7H) Read/Write Read modify After reset write Functions instructions are prohibited. 010: (1 + N) waits 110 Invalid settings Master enable bit 0 16-Mbyte area 1 CS area enable CS2 area selection 0 1 16-Mbyte area Specified address area Number of address area waits (See 3.6.2 (3) "Wait control".) Data bus width selection 0 1 16-bit data bus 8-bit data bus Figure 3.6.5 Chip Select/Wait Control Registers 91CW18A-84 2005-08-15 TMP91CW18A (1) Master enable bits Bit7 ( Table 3.6.2 Dynamic Bus Sizing Operand Data Bus Width Operand Start Address 2n + 0 8 bits (Even number) 2n + 1 (Odd number) 2n + 0 (Even number) 16 bits 2n + 1 (Odd number) Memory Data Bus Width 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 2n + 0 (Even number) 8 bits 16 bits 32 bits 8 bits 2n + 1 (Odd number) 16 bits 2n + 2 2n + 4 Input data in bit positions marked xxxxx is ignored during a read. During a write, the bus lines corresponding to these bit positions go high-impedance and the write strobe signal for the bus remains inactive. 91CW18A-85 2005-08-15 TMP91CW18A (3) Wait control Bits 0 to 2 ( 000 001 010 Number of Waits 2 waits 1 wait (1 + N) waits Wait Operation Inserts a wait of two states, irrespective of the WAIT pin state. Inserts a wait of one state, irrespective of the WAIT pin state. Inserts one wait state, then continuously samples the state of the WAIT pin. While the WAIT pin remains low, the wait continues; the bus cycle is prolonged until the pin goes high. Ends the bus cycle without a wait, regardless of the WAIT pin state. 011 0 waits A Reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Clearing B2CS 91CW18A-86 2005-08-15 TMP91CW18A Setting example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H ..............Start address: 010000H MAMR0 = 07H .............Address area: 64 Kbytes B0CS = 83H .................ROM/SRAM, 16-bit data bus, 0 waits, CS0 area settings enabled 91CW18A-87 2005-08-15 TMP91CW18A 3.6.3 Connecting External Memory Figure 3.6.6 shows an example of how to connect external memory to the TMP91CW18A. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. External decoder circuit 74AC573 TMP91CW18A A16 to A23 DQ LE CS Address bus DQ ALE AD8 to AD15 LE Upper byte ROM OE CS Lower byte ROM OE CS 8-bit RAM CS 8-bit I/O OE WE OE WE AD0 to AD7 RD WR Figure 3.6.6 Example of External Memory Connection (ROM uses 16-bit bus: RAM and I/O use 8-bit bus.) Since the MCU has no CS pins, user have to make chip select signals by making a external address decoder circuit in order to control external memory area which is decided by memory start address register and memory address mask register. 91CW18A-88 2005-08-15 TMP91CW18A 3.7 8-Bit Timer (TMRA) The TMP91CW18A features eight built-in 8-bit timer. These timers are paired into four modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each module consists of two channels and can operate in any of the following four operating modes. * * * * 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) 8-bit programmable square wave pulse generation output mode (PPG - variable duty cycle with variable period) (1 timer) 8-bit pulse width modulation output mode (PWM - variable duty cycle with constant period) (1 timer) Figure 3.7.1 to Figure 3.7.4 show block diagrams for TMRA01, TMRA23, TMRA45 and TMRA67. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five control SFRs (Special function registers). Each of the four modules (TMRA01, TMRA23, TMRA45 and TMRA67) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter is as follows. 3.7.1 3.7.2 3.7.3 3.7.4 Block Diagrams Operation of Each Circuit SFRs Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Setting for each mode Table 3.7.1 Registers and Pins for Each Module Module Input pin for external clock Output pin for timer flip-flop Timer run register Timer register SFR (Address) Timer mode register Timer flip-flop control register TA1OUT (Shared with P70) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TA3OUT (Shared with P71) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TA5OUT (Shared with P72) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) TMRA01 TMRA23 TMRA45 TMRA67 TA6IN (Shared with P35) TA7OUT (Shared with P36) TA67RUN (0118H) TA6REG (011AH) TA7REG (011BH) TA67MOD (011CH) TA7FFCR (011DH) External pin 91CW18A-89 2005-08-15 3.7.1 Prescaler 2 T1 Timer flip-flop TA1FF Selector T1 T4 T16 8-bit up counter (UC0) overflow Prescaler clock: T0 4 T4 T16 T256 8 16 32 64 128 256 512 Block Diagrams Run/clear TA01RUN TA01RUN TA01RUN Timer flip-flop output: TA1OUT 2n Figure 3.7.1 TMRA01 Block Diagram TA01MOD 91CW18A-90 8-bit up counter (CP0) TA01MOD Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG TMRA0 Internal data bus TMRA1 match output: interrupt output: TA0TRG INTTA1 TMP91CW18A 2005-08-15 Prescaler Prescaler clock: T0 2 T1 T4 T16 T256 Timer flip-flop TA3FF Selector Selector T1 T16 T256 TA23MOD Figure 3.7.2 TMRA23 Block Diagram 91CW18A-91 Match 8-bit comparator detect (CP2) TA2TRG TA23MOD 8-bit timer register (CP3) Match detect 8-bit timer register TA3REG TMRA2 Internal data bus TMRA3 match output: interrupt output: TA2TRG INTTA3 TMP91CW18A 2005-08-15 Prescaler Prescaler clock: T0 2 T1 T4 T16 T256 Timer flip-flop TA5FF Selector T1 T4 T16 8-bit up counter (UC4) 2n overflow TA45MOD |